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<title>CMSIS-Core (Cortex-M): PMU_Type Struct Reference</title>
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   <div id="projectname">CMSIS-Core (Cortex-M)
   &#160;<span id="projectnumber">Version 5.6.0</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">PMU_Type Struct Reference<div class="ingroups"><a class="el" href="group__pmu8__functions.html">PMU Functions for Armv8.1-M</a></div></div>  </div>
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<p>Structure type to access the Performance Monitoring Unit (PMU).  
 <a href="structPMU__Type.html#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a08f877e8edcb1c19b81ebcf95f85e2f7"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a08f877e8edcb1c19b81ebcf95f85e2f7">EVCNTR</a> [<a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">__PMU_NUM_EVENTCNT</a>]</td></tr>
<tr class="memdesc:a08f877e8edcb1c19b81ebcf95f85e2f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Event Counter Registers.  <a href="#a08f877e8edcb1c19b81ebcf95f85e2f7">More...</a><br/></td></tr>
<tr class="separator:a08f877e8edcb1c19b81ebcf95f85e2f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada85996bd815d9eff9552794feec6d74"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#ada85996bd815d9eff9552794feec6d74">CCNTR</a></td></tr>
<tr class="memdesc:ada85996bd815d9eff9552794feec6d74"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Cycle Counter Register.  <a href="#ada85996bd815d9eff9552794feec6d74">More...</a><br/></td></tr>
<tr class="separator:ada85996bd815d9eff9552794feec6d74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27682a8d2fe09d2052a4295d5b4a243b"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a27682a8d2fe09d2052a4295d5b4a243b">EVTYPER</a> [<a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">__PMU_NUM_EVENTCNT</a>]</td></tr>
<tr class="memdesc:a27682a8d2fe09d2052a4295d5b4a243b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Event Type and Filter Registers.  <a href="#a27682a8d2fe09d2052a4295d5b4a243b">More...</a><br/></td></tr>
<tr class="separator:a27682a8d2fe09d2052a4295d5b4a243b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a61fea523ea0f4e9242101cb09fc6f6a8"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a61fea523ea0f4e9242101cb09fc6f6a8">CCFILTR</a></td></tr>
<tr class="memdesc:a61fea523ea0f4e9242101cb09fc6f6a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Cycle Counter Filter Register.  <a href="#a61fea523ea0f4e9242101cb09fc6f6a8">More...</a><br/></td></tr>
<tr class="separator:a61fea523ea0f4e9242101cb09fc6f6a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a030ee86cd33b72a0c5e66fbaf418d1be"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a030ee86cd33b72a0c5e66fbaf418d1be">CNTENSET</a></td></tr>
<tr class="memdesc:a030ee86cd33b72a0c5e66fbaf418d1be"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Count Enable Set Register.  <a href="#a030ee86cd33b72a0c5e66fbaf418d1be">More...</a><br/></td></tr>
<tr class="separator:a030ee86cd33b72a0c5e66fbaf418d1be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3c24c882b1679390b1dd957dbd0f0bf6"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a3c24c882b1679390b1dd957dbd0f0bf6">CNTENCLR</a></td></tr>
<tr class="memdesc:a3c24c882b1679390b1dd957dbd0f0bf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Count Enable Clear Register.  <a href="#a3c24c882b1679390b1dd957dbd0f0bf6">More...</a><br/></td></tr>
<tr class="separator:a3c24c882b1679390b1dd957dbd0f0bf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f5a5872105d9056145e9095bc1c63ac"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a3f5a5872105d9056145e9095bc1c63ac">INTENSET</a></td></tr>
<tr class="memdesc:a3f5a5872105d9056145e9095bc1c63ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Interrupt Enable Set Register.  <a href="#a3f5a5872105d9056145e9095bc1c63ac">More...</a><br/></td></tr>
<tr class="separator:a3f5a5872105d9056145e9095bc1c63ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaff7d5f3246c641d1f503d74a5adb0ee"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#aaff7d5f3246c641d1f503d74a5adb0ee">INTENCLR</a></td></tr>
<tr class="memdesc:aaff7d5f3246c641d1f503d74a5adb0ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Interrupt Enable Clear Register.  <a href="#aaff7d5f3246c641d1f503d74a5adb0ee">More...</a><br/></td></tr>
<tr class="separator:aaff7d5f3246c641d1f503d74a5adb0ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2acdf96dc7f60ad5a384d1f47e0bb8e0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a2acdf96dc7f60ad5a384d1f47e0bb8e0">OVSCLR</a></td></tr>
<tr class="memdesc:a2acdf96dc7f60ad5a384d1f47e0bb8e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Overflow Flag Status Clear Register.  <a href="#a2acdf96dc7f60ad5a384d1f47e0bb8e0">More...</a><br/></td></tr>
<tr class="separator:a2acdf96dc7f60ad5a384d1f47e0bb8e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2add0abae68f27801299d6dd4bfcde66"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a2add0abae68f27801299d6dd4bfcde66">SWINC</a></td></tr>
<tr class="memdesc:a2add0abae68f27801299d6dd4bfcde66"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Software Increment Register.  <a href="#a2add0abae68f27801299d6dd4bfcde66">More...</a><br/></td></tr>
<tr class="separator:a2add0abae68f27801299d6dd4bfcde66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a153e694a19f845e65a3d2abd4d64faa7"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a153e694a19f845e65a3d2abd4d64faa7">OVSSET</a></td></tr>
<tr class="memdesc:a153e694a19f845e65a3d2abd4d64faa7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Overflow Flag Status Set Register.  <a href="#a153e694a19f845e65a3d2abd4d64faa7">More...</a><br/></td></tr>
<tr class="separator:a153e694a19f845e65a3d2abd4d64faa7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1f2e763ceeeff8ff15c0bd3520b683e8"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a1f2e763ceeeff8ff15c0bd3520b683e8">TYPE</a></td></tr>
<tr class="memdesc:a1f2e763ceeeff8ff15c0bd3520b683e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Type Register.  <a href="#a1f2e763ceeeff8ff15c0bd3520b683e8">More...</a><br/></td></tr>
<tr class="separator:a1f2e763ceeeff8ff15c0bd3520b683e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba9bddd6b49c88e38f4bb79d32002c3c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#aba9bddd6b49c88e38f4bb79d32002c3c">CTRL</a></td></tr>
<tr class="memdesc:aba9bddd6b49c88e38f4bb79d32002c3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Control Register.  <a href="#aba9bddd6b49c88e38f4bb79d32002c3c">More...</a><br/></td></tr>
<tr class="separator:aba9bddd6b49c88e38f4bb79d32002c3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a60a8296d51236329e79d1604080aa9c1"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a60a8296d51236329e79d1604080aa9c1">AUTHSTATUS</a></td></tr>
<tr class="memdesc:a60a8296d51236329e79d1604080aa9c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Authentication Status Register.  <a href="#a60a8296d51236329e79d1604080aa9c1">More...</a><br/></td></tr>
<tr class="separator:a60a8296d51236329e79d1604080aa9c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a439c7a309f02c41a6581d0819e896fdc"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a439c7a309f02c41a6581d0819e896fdc">DEVARCH</a></td></tr>
<tr class="memdesc:a439c7a309f02c41a6581d0819e896fdc"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Device Architecture Register.  <a href="#a439c7a309f02c41a6581d0819e896fdc">More...</a><br/></td></tr>
<tr class="separator:a439c7a309f02c41a6581d0819e896fdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aac8b7bca579afd4969d8bfffa61afbed"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#aac8b7bca579afd4969d8bfffa61afbed">DEVTYPE</a></td></tr>
<tr class="memdesc:aac8b7bca579afd4969d8bfffa61afbed"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Device Type Register.  <a href="#aac8b7bca579afd4969d8bfffa61afbed">More...</a><br/></td></tr>
<tr class="separator:aac8b7bca579afd4969d8bfffa61afbed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe4612a6387c5be0e56898bfa6b16902"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#abe4612a6387c5be0e56898bfa6b16902">PIDR4</a></td></tr>
<tr class="memdesc:abe4612a6387c5be0e56898bfa6b16902"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Peripheral Identification Register 4.  <a href="#abe4612a6387c5be0e56898bfa6b16902">More...</a><br/></td></tr>
<tr class="separator:abe4612a6387c5be0e56898bfa6b16902"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe7c3069b9a30d54e5e30166a2281bd7"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#afe7c3069b9a30d54e5e30166a2281bd7">PIDR0</a></td></tr>
<tr class="memdesc:afe7c3069b9a30d54e5e30166a2281bd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Peripheral Identification Register 0.  <a href="#afe7c3069b9a30d54e5e30166a2281bd7">More...</a><br/></td></tr>
<tr class="separator:afe7c3069b9a30d54e5e30166a2281bd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a764266e9b41e7c100a9853889d94ab"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a8a764266e9b41e7c100a9853889d94ab">PIDR1</a></td></tr>
<tr class="memdesc:a8a764266e9b41e7c100a9853889d94ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Peripheral Identification Register 1.  <a href="#a8a764266e9b41e7c100a9853889d94ab">More...</a><br/></td></tr>
<tr class="separator:a8a764266e9b41e7c100a9853889d94ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f7053542f392f435ad51930d0504622"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a2f7053542f392f435ad51930d0504622">PIDR2</a></td></tr>
<tr class="memdesc:a2f7053542f392f435ad51930d0504622"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Peripheral Identification Register 2.  <a href="#a2f7053542f392f435ad51930d0504622">More...</a><br/></td></tr>
<tr class="separator:a2f7053542f392f435ad51930d0504622"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a831a9b4e2e07eef0b93713beb26a6516"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a831a9b4e2e07eef0b93713beb26a6516">PIDR3</a></td></tr>
<tr class="memdesc:a831a9b4e2e07eef0b93713beb26a6516"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Peripheral Identification Register 3.  <a href="#a831a9b4e2e07eef0b93713beb26a6516">More...</a><br/></td></tr>
<tr class="separator:a831a9b4e2e07eef0b93713beb26a6516"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a54117364a5e8d3af0cc45769bb9b11c7"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a54117364a5e8d3af0cc45769bb9b11c7">CIDR0</a></td></tr>
<tr class="memdesc:a54117364a5e8d3af0cc45769bb9b11c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Component Identification Register 0.  <a href="#a54117364a5e8d3af0cc45769bb9b11c7">More...</a><br/></td></tr>
<tr class="separator:a54117364a5e8d3af0cc45769bb9b11c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0eded5a42f8b81a09df17ce0a9f90897"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a0eded5a42f8b81a09df17ce0a9f90897">CIDR1</a></td></tr>
<tr class="memdesc:a0eded5a42f8b81a09df17ce0a9f90897"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Component Identification Register 1.  <a href="#a0eded5a42f8b81a09df17ce0a9f90897">More...</a><br/></td></tr>
<tr class="separator:a0eded5a42f8b81a09df17ce0a9f90897"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94fa4cd97b83324090d6e696f3568415"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#a94fa4cd97b83324090d6e696f3568415">CIDR2</a></td></tr>
<tr class="memdesc:a94fa4cd97b83324090d6e696f3568415"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Component Identification Register 2.  <a href="#a94fa4cd97b83324090d6e696f3568415">More...</a><br/></td></tr>
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<tr class="memitem:aff7ed1b5979deb4fb0a536aa477c6830"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structPMU__Type.html#aff7ed1b5979deb4fb0a536aa477c6830">CIDR3</a></td></tr>
<tr class="memdesc:aff7ed1b5979deb4fb0a536aa477c6830"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMU Component Identification Register 3.  <a href="#aff7ed1b5979deb4fb0a536aa477c6830">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure type to access the Performance Monitoring Unit (PMU). </p>
</div><h2 class="groupheader">Field Documentation</h2>
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<p>PMU Authentication Status Register. </p>
<p>Offset: 0xFB8 (R/W) </p>

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<p>PMU Cycle Counter Filter Register. </p>
<p>Offset: 0x47C (R/W) </p>

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<p>PMU Cycle Counter Register. </p>
<p>Offset: 0x7C (R/W) </p>

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<p>PMU Component Identification Register 0. </p>
<p>Offset: 0xFF0 (R/W) </p>

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<p>PMU Component Identification Register 1. </p>
<p>Offset: 0xFF4 (R/W) </p>

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<p>PMU Component Identification Register 2. </p>
<p>Offset: 0xFF8 (R/W) </p>

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<p>PMU Component Identification Register 3. </p>
<p>Offset: 0xFFC (R/W) </p>

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<p>PMU Count Enable Clear Register. </p>
<p>Offset: 0xC20 (R/W) </p>

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<p>PMU Count Enable Set Register. </p>
<p>Offset: 0xC00 (R/W) </p>

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<p>PMU Control Register. </p>
<p>Offset: 0xE04 (R/W) </p>

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<p>PMU Device Architecture Register. </p>
<p>Offset: 0xFBC (R/W) </p>

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<p>PMU Device Type Register. </p>
<p>Offset: 0xFCC (R/W) </p>

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<p>PMU Event Counter Registers. </p>
<p>Offset: 0x0 (R/W)</p>
<p>Two up to 31 event counters, see device specific <a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">__PMU_NUM_EVENTCNT</a> </p>

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<p>PMU Event Type and Filter Registers. </p>
<p>Offset: 0x400 (R/W)</p>
<p>Two up to 31 event counters, see device specific <a class="el" href="group__device__config.html#ga9d4c51d9ca3eae58635d1040a3fb5fd2">__PMU_NUM_EVENTCNT</a> </p>

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<p>PMU Interrupt Enable Clear Register. </p>
<p>Offset: 0xC60 (R/W) </p>

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<p>PMU Interrupt Enable Set Register. </p>
<p>Offset: 0xC40 (R/W) </p>

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<p>PMU Overflow Flag Status Clear Register. </p>
<p>Offset: 0xC80 (R/W) </p>

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<p>PMU Overflow Flag Status Set Register. </p>
<p>Offset: 0xCC0 (R/W) </p>

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<p>PMU Peripheral Identification Register 0. </p>
<p>Offset: 0xFE0 (R/W) </p>

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<p>PMU Peripheral Identification Register 1. </p>
<p>Offset: 0xFE4 (R/W) </p>

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<p>PMU Peripheral Identification Register 2. </p>
<p>Offset: 0xFE8 (R/W) </p>

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<p>PMU Peripheral Identification Register 3. </p>
<p>Offset: 0xFEC (R/W) </p>

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<p>PMU Peripheral Identification Register 4. </p>
<p>Offset: 0xFD0 (R/W) </p>

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<p>PMU Software Increment Register. </p>
<p>Offset: 0xCA0 (R/W) </p>

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<p>PMU Type Register. </p>
<p>Offset: 0xE00 (R/W) </p>

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